The present invention relates to a method of decoding binary signals processed according to an error correcting convolution code, wherein binary operations form branch metrics and they again form path metrics according to the Viterbi decoding proces for the reception probability of the source data binary signals formed in the encoder.
This method and decoders operating according to this method are disclosed, for example, in IEEE Transactions on Communications, Vol. COM-26, No. 10, October, 1978, pages 1463-1470; IEEE Transactions on Communication Technology, Vol. COM-19, No. 5, October, 1971, pages 835-848; NTC, Vol. 3, 1981, E1.7.1-E1.7.4; EP No. 127,984. A2; EP No. 52,463.A1; EP No. 54,583.
During the transmission of binary data signals, error correcting methods are often employed. One such method employs Viterbi coding at the transmitter and a corresponding Viterbi decoding at the receiver. Viterbi coding and decoding involves a so-called forward error correction, which means that no return receipt is required from the receiver to the transmitter. This is of advantage particularly for data transmission by means of satellites.
If the data source does not furnish inherent signals including natural redundancy, a correction criterion in the form of artificial time redundancy of the channel bits must be provided. Viterbi coding employs convolutional codes which derive time dependent information sequences from unique source signal processes. These information sequences are transmitted and correspondingly decoded at the receiver.
The decoders described in the above-mentioned publications are composed of networks including decision logics and calculating mechanisms for the determination of branch and path metrics according to the laws of Viterbi decoding, registers and memories for the intermediate storage of path metric information and output units for providing the decoded binary signals with the aid of decision criteria. A Viterbi decoder operating in VLSI (very large scale integrated) form is disclosed in NTC, Vol. 3, supra. In its ACS (add - compare - select) network for calculating the path metrics, many, specifically 27, gate planes, or logic levels, exist which lead to long signal delays.